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Netclasses for gschem -- some thoughts

Currently we draw schematics in gschem. What we get for PCB layout is a collection of elements (footprints) and a netlist indicating all intended electrical connections.

There is no guidance for the physical layout. We are completely free in positioning elements and for trace parameters. This means that only smart and carefully working people can do larger, non trivial layouts. No chance for unskilled people or autorouters.

But we may consider to define net attributes or net classes (a net class is a collection of multiple net attributes) in the schematic. This way we get restrictions for the PCB layout, which prevents layout errors and makes the layout process easier and faster. We can concentrate on finding a good routing, trace parameters are predefined from the schematic. Here is a picture of a piece of a schematic with four net classes:

Here we have these net classes: Power, Bypass, Short, and FiftyOhm. Additional we should have a default net class, which defines initial values for all nets. This ways we can draw our schematics with default class for all nets, and modify important nets segments with special classes later. We can define arbitrary net classes and assign these classes to subnets.

Class attributes may include: (Min)_Trace_Width, (Max)_Trace_Length, Clearance, Max_Resistance, Impedance, Min_Current, PCB_Layer, Color, ... (Classes with restricted trace length may be marked with special rats nest lines in PCB, and length is checked in DRC.)

For the layout process each pad or pin has an assigned net class -- we can start drawing traces there without worrying about trace parameters. One special case are pads and pins where multiple net classes join (P1 in above picture). If we start traces there then we have to choose amongst multiple classes, for example with the help of a popup menu or by clicking on one pin/pad of desired class.

It may be a good idea to have the possibility to make a net class compatible with other classes: For the above picture, we have net class "Bypass" connecting the OpAmp and the capacitor. (This may limit the trace length). If netclass "Bypass" is not compatible with netclass "Power", then both nets can only join at point P1 (this node is common to both subnets). Indeed this layout may be what we want to enforce. But we may relax the layout by making netclass "Bypass" compatible with netclass "Supply". This still enforce a connection of netclass "Bypass" from OpAmp to capacitor (for example restricting trace length), but for this case the power net can be connected at an arbitrary point to the "Bypass" net.

More or less related to this problem are attributes defining pairs of traces for differential signals: Maybe we can assign attributes like "SigA@1" and "SigA@2" indicating the pair, which should have a defined trace separation and equal length on PCB board. (A similar notation may be useful to indicate buses and allow pinswap in the schematic).

Defining all these parameters on the schematic level should take not too much time, but layout work should become much easier and faster and number of layout bugs should be smaller. And the autoplacer can use the restrictions implied by the maximum trace length for initial position of elements, and the autorouter has nearly all necessary information. The human only has to define layer stack, dimensions of PCB board, and position of a few key elements. Maybe additional a few polygons...